The present invention relates to the field of electronic circuits, and, more particularly, to low-power comparison devices. The present invention is particularly well suited for applications in which power consumption is limited, especially in electronic equipment powered by a battery.
One application in which comparison devices with low power consumption are used is the biomedical field, such as in portable equipment or sensors. In this application, the electronic equipment should consume as little power as possible because the total current available is very limited. One microampere typically corresponds to an available order of magnitude.
When the consumption of an electronic device is reduced, its performance characteristics are generally reduced as well. This is especially the case with comparison devices. To reduce their consumption, the bias current is typically reduced. Yet, the more the bias current is reduced, the lower the efficiency of these devices. That is, their switch-over operation becomes very slow. For example, a standard prior art comparator, biased at 60 microamperes, switches over in about one hundred nanoseconds. When biased at 500 nanoamperes, it will switch over in six microseconds.
A prior art comparison device for comparing two weak signals M1 and P1 applied at its input is shown in FIG. 1 in an exemplary metal oxide semiconductor (MOS) technology embodiment. In general, one of the two signals is a reference signal. The signal MI is a reference signal with a level assumed to be constant, and the signal PI is a signal with a variable level given by any unspecified electronic circuit (not shown). This circuit may, for example, be a measurement circuit.
When weak signals have to be compared, the comparison device usually includes two series-connected comparators, namely a first comparator to amplify the signals to be compared followed by a second comparator with a very high gain. The comparison device illustrated in FIG. 1 thus includes a first comparator COMP1 with differential outputs A and B followed by a second comparator COMP2 with very high gain that delivers a logic signal OUT at its output. The output logic level indicates which of the input signals MI or PI is greater than the other one.
The signal MI is applied to the non-inverting input e+ of the first comparator and the signal PI is applied to the inverting input exe2x88x92. The first arm of the comparator COMP1, associated with the non-inverting input e+, includes a first MOS transistor M1 mounted as a diode with its gate and drain connected. The first MOS transistor M1 is series-connected with a second MOS transistor M2 between the power supply voltage VPLUS and a current bias node N1. The second transistor M2 receives the signal MI at its gate. The second arm of the comparator COMP1, associated with the inverting input exe2x88x92, similarly includes a first MOS transistor M3 mounted as a diode with its gate and drain connected. The first MOS transistor M3 is series-connected with a second MOS transistor M4 between the power supply voltage VPLUS and the current bias node N1. The second transistor M4 receives the signal PI at its gate.
The comparator COMP1 further includes a current generator 1 connected between the bias node N1 and the power supply voltage VMINUS. In this configuration, if the level of the signal MI is greater than that of the signal PI, the current in the first arm of the comparator COMP1 gradually rises from 0 to the bias current level Ip1 (which the current generator 1 can provide) while no current flows in the second arm.
The very-high-gain comparator COMP2, which is not illustrated in detail in FIG. 1, includes a first amplifier stage with differential inputs followed by a direction stage and an output stage to reshape the signal. The differential input amplifier stage is biased by a current Ip2 given by a current generator. In practice, Ip1 may be equal to Ip2. Thus, in the second comparator COMP2, since the current Ip2 is also very low (i.e., in the range of 500 nanoamperes), the switch-over is also very slow.
An object of the invention is to improve the switch-over performance characteristics of a comparator under low bias current.
Yet another object of the invention is to provide a very low power comparison device with improved switch-over speed.
Referring again to FIG. 1, the basic idea of the invention is to use the current flowing into an arm of the first comparator and apply it with a multiplier coefficient to the second comparator as a complement of the current Ip2. Thus, the switch-over is accelerated in the second comparator, enabling a substantial improvement of the performance characteristics of the comparison device. Thus, if a device is provided within the comparison device for copying and providing an additional supply of current from the first arm of the comparator COMP2 as an additional bias current in the comparator COMP2, the corresponding switch-over is accelerated to a signal level PI which becomes lower than that of the signal MI.
To accelerate the reverse switch-over, when the level of the signal PI becomes greater than that of the signal MI, it is necessary to provide a similar device on the other arm of the comparator COMP1. Once the comparator COMP2 has changed over, the bias current is again at its maximum level, corresponding to the sum of the bias current Ip2 of the second comparator and the bias current Ip1 of the first comparator multiplied by the multiplier factor K. Since there is no need for the current outside the zones close to the switch-over, each additional current supply device may be cut off as soon as the output of the comparison device has changed over to the corresponding direction. Thus, for each additional-current supply device, a switch controlled by the appropriate logic level of the output signal of the comparison device may be used.
According to the invention, a device for comparing two input signals includes a first comparator with differential outputs to whose inputs the signals are applied. The first comparator is followed by a second comparator delivering an output logic signal of the device. Each comparator includes at least one input differential stage, and each stage has two arms biased by a bias current generator. The comparison device may also include at least one additional current supply circuit associated with an arm of the input differential stage of the first comparator to copy the current of the arm and add it, with a multiplier factor, to the bias current of the input differential stage of the second comparator. This facilitates a corresponding switch-over.